1. Field of the Invention
The present invention relates to a capacitor for a semiconductor device and a method of forming the same. More particularly, the present invention relates to an improved capacitor having a high capacitance and a method of forming the same.
2. Description of the Related Art
Recently, as information media such as computers have become widely used, the semiconductor industry has made great strides in the development of the information media products. Functionally, semiconductor devices with a large storage capacity are required to operate at a very high speed. Accordingly, semiconductor technology has improved the degree of integration, the reliability, and the response capability in order to increase the operating speed of semiconductor devices.
A dynamic random access memory (DRAM) has been the most widely used semiconductor memory device because of its ability to randomly read/write data, and its high storage capacity. In general, a DRAM device includes a memory cell region to store data as an electric charge, and a peripheral circuit region through which data is transferred as an electrical signal. The memory cell usually includes an access transistor and a storage capacitor.
The size of the capacitor has been reduced as the degree of integration of the memory devices has increased. Research has been widely conducted for a method of manufacturing a smaller, high-capacitance capacitor. In particular, a method of increasing the capacitance without increasing the capacitor's surface size has been studied in recent years.
The capacitance can be increased by: (1) increasing the surface area of the storage electrode, i.e., the lower electrode of the capacitor; (2) reducing the thickness of the dielectric layer; and/or (3) increasing the dielectric constant of the dielectric layer.
Conventionally, metal oxides such as Ta2O5, TiO2, Al2O3, Y2O3, ZrO2, HfO2, BaTiO3 and SrTiO3 have been used for the dielectric layer because of their high dielectric constants, as disclosed in U.S. Pat. No. 5,316,982, issued to Taniguchi et al. However, reducing the thickness of the dielectric layer has its own limits in view of the high degree of integration of the memory device. In addition, although various high dielectric constant materials, and various methods for manufacturing dielectric layers using the same, are widely known, it is difficult to adapt the dielectric materials in manufacturing the dielectric layer.
Accordingly, increasing the surface area of the storage electrode has been regarded as the most efficient method of improving the capacitance of a capacitor.
To increase the surface area of a storage electrode, the capacitor has developed from an initial plane structure to a stack structure or a trench structure, and from the stack structure to a cylindrical structure or a fin structure. For example, U.S. Pat. No. 5,656,536 discloses a conventional stacked structure capacitor having a crown shape; and U.S. Pat. No. 5,716,884 and U.S. Pat. No. 5,807,782 disclose other conventional stacked structure capacitors having a fin shape. U.S. Pat. No. 5,877,052 discloses a conventional method of increasing the capacitance by forming a hemispherical grain (HSG) layer on a storage electrode of a capacitor; and U.S. Pat. No. 5,956,587 discloses yet another conventional method of forming a HSG layer on a storage electrode having a cylindrical shape using above-mentioned methods.
However, the conventional methods of increasing the capacitance using the HSG layer has problems because a critical dimension (CD) between storage electrodes cannot be reduced to a desirable degree, and the HSG layer is often separated from the storage electrode to generate a process failure between two adjacent storage electrodes known as a “bridge”. Accordingly, the conventional methods described above have many problems in forming capacitors with a design rule less than about 0.14 μm. Therefore, a cylindrical shaped capacitor with an increased height has been mainly used.
Example of a method of forming the cylindrical capacitor is generally disclosed in U.S. Pat. No. 6,657,377.
FIGS. 1A and 1B are cross sectional views illustrating a conventional method for forming a one-cylinder-stack (OCS) structured capacitor.
Referring to FIG. 1A, an insulating interlayer 12 is formed on a semiconductor substrate 10, and a contact hole 14 is formed by partially etching insulating interlayer 12, to expose a conductive region such as a source region (not shown) of semiconductor substrate 10. Then, a conductive material such as a doped polysilicon is filled into contact hole 14, to form a storage node contact plug 16.
An etching stop layer 18 of nitride, and a mold layer 20 of oxide are sequentially formed on insulating interlayer 12 and storage node contact plug 16. Subsequently, mold layer 20 and etching stop layer 18 are etched by an etching process, to form a storage node hole 22 to expose storage node contact plug 16.
A storage electrode layer 26 such as a polysilicon layer is formed on the bottom and sidewalls of storage node hole 22 and on the top surface of mold layer 20, and an oxide material is formed on storage electrode layer 26 to a sufficient thickness to fill storage node hole 22, thereby forming a sacrificial layer 24.
Sacrificial layer 24 and storage electrode layer 26 are removed to expose mold layer 20 by an etch back process or a chemical mechanical polishing (CMP) process, to form storage electrode 26 separated in accordance with each node of a memory device.
Referring to FIG. 1B, any residual of sacrificial layer 24 remaining in storage node hole 22 and mold layer 20 is removed by a wet etching process.
According to the conventional method described above, the height of the storage electrode is high to increase the capacitance, thus mold layer 20 is formed as thick as possible. In general, the thicker the mold layer 20, the greater the slope of storage node hole 22. Accordingly, the critical dimension (CD) around a bottom portion of storage node hole 22 is very small. A bottom portion of storage electrode 26, which is formed shallow and high, is narrow relative to a top portion of the storage electrode. Thermal stress generated in subsequent processes causes weak storage electrodes to break, thus creating bridge failures between two adjacent cells as depicted by reference numeral 28 in FIG. 1B. That is, a process failure is generated over two unit cells (2-bit failure).
In addition, the higher the storage electrode, the greater the step difference between a capacitor region and a non-capacitor region of a substrate, creating difficulties in the subsequent processes.
Korean Publication Patent No. 2003-75907 discloses forming at least one mold layer and at least one support having different etching rates, prior to performing an etching process to form a storage node hole. Therefore, the support prevents the storage electrode from breaking. However, this Patent has disadvantages in that additional processes are required to form the support such as a deposition process and an etching process. And also the processes to form the insulating interlayer disposed between the conductive structure and the storage electrode are very complicated.